电子工程专辑

Cadence验证方案广受青睐，SystemVerilog成主流开发技术

Cadence设计系统公司近日宣布，该公司基于SystemVerilog的验证解决方案在去年迅猛发展，用该语言进行试验的客户从大约40家增加到了150家，他们将该语言应用于创建功能原型项目，或者应用到主流产品开发。 Cadence设计系统公司近日宣布，该公司基于SystemVerilog ...
电子工程专辑

一图读懂：VHDL、Verilog与SystemVerilog的区别与联系，哪个更适合你？

VHDL或Verilog，system verilog这三种语言的区别与联系，各自优势。这是一个初学者最常见的问题。其实这三种语言的差别并不大，他们的描述能力也是类似的。掌握其中一种语言以后，可以通过短期的学习，较快的学会另一种语言，掌握了verilog HDL学System Verilog则更 ...
EDN

Commentary: SystemVerilog enables design with verification

The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...
Design-Reuse

Denali and Mentor Team Up to Enable Verification IP for SystemVerilog Verification Environments

Palo Alto, Calif., May 31, 2007 —Denali Software, Inc., and Mentor Graphics Corporation (Nasdaq: MENT) today announced the availability of Denali's PureSpec™ verification IP products that are ...
Design-Reuse

Randsequence: SystemVerilog's unsung hero

Constrained random verification, for quite some time now, has been the default verification methodology for complex ASIC/SoC designs. Central to this methodology is the process of letting the ...
Electronic Design

Simulator Adds Assertion IP And Native SystemVerilog Support

The latest release of the VCS verification environment sports new capabilities that help users find more bugs more quickly, with up to a fivefold increase in verification speed (see the figure). Key ...
EDN

IEEE approves SystemVerilog, revision of Verilog

SAN FRANCISCO — The IEEE Wednesday (Nov. 8) said it has approved standards for hardware description languages SystemVerilog and Verilog. The Verilog standard, IEEE 1364-2005, is a revision to the ...
Electronic Design

Cadence, Mentor Team To Open Up SystemVerilog Verification

When the SystemVerilog hardware description language (HDL) came onto the scene a few years ago, it promised true openness and interoperability. Here, crowed the hype, was an HDL that would enable ...
Business Wire

SpringSoft’s Verdi Debug Software Expands Verification Interoperability with ...

HSINCHU, Taiwan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its ...